surface mount resettable ptcs revision october 18, 2015 1 / 3 @ un semiconductor co., ltd. 2015 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. the smd2018 series ptc provides surface mount over-current protection for applications where space is at a premium and reset table protection is desired. ? rohs compliant, lead-free and halogen-free ? fast time-to-trip ? compact design saves board space ? agency recognition: ul ? low-profile almost anywhere there is a low voltage power supply, up to 30v and a load to be protected, including: ? computer mother board, modem. usb hub ? pdas & charger, analog & digital line card ? digital cameras, disk drivers, cd-roms ? power ports ? general electronics part number i hold (a) i trip (a) v max (vdc) i max (a) p dtyp. (w) maximum time to trip resistance current (a) time (sec.) r min () r max () SMD2018-030 0.30 0.60 60 100 0.90 1.50 3.00 0.500 2.300 smd2018-050 0.55 1.20 60 100 1.00 2.50 3.00 0.200 1.000 smd2018-100 1.10 2.20 15 100 1.10 8.00 0.40 0.060 0.360 smd2018-150 1.50 3.00 15 100 1.10 8.00 0.80 0.050 0.170 smd2018-200 2.00 4.00 10 100 1.10 8.00 2.40 0.030 0.100 i hold = hold current: maximum current device will pass without tripping in 25c still air. i trip = trip current: minimum current at which the device will trip in 25c still air. v max = maximum voltage device can withstand without damage at rated current (i max ) i max = maximum fault current device can withstand without damage at rated voltage (v max ) p dtyp. = power dissipated from device when in the tripped state at 25c still air. r min = minimum resistance of device in initial (un-soldered) state. r max = maximum resistance of device in initial (un-soldered) state. r 1max = maximum resistance of device at 25c measured one hour after tripping. caution: operation beyond the speci?ed rating may result in damage and possible arcing and flame.
surface mount resettable ptcs revision october 18, 2015 2 / 3 @ un semiconductor co., ltd. 2015 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. part number ambient operation temperature -40c -20c 0c 25c 40c 50c 60c 70c 85c hold current (a) SMD2018-030 0.48 0.42 0.35 0.30 0.24 0.21 0.17 0.15 0.10 smd2018-050 0.87 0.77 0.67 0.55 0.46 0.41 0.36 0.31 0.23 smd2018-100 1.71 1.52 1.32 1.10 0.94 0.84 0.74 0.64 0.50 smd2018-150 2.38 2.10 1.82 1.50 1.27 1.13 0.99 0.85 0.64 smd2018-200 2.95 2.65 2.35 2.00 1.74 1.59 1.44 1.29 1.06 enviro nmental specificatio ns conditions resistance change passive aging +85c, 1000 hrs. 5% typical humidity aging +85c, 85% r.h. , 168 hours 5% typical thermal shock +85c to -40c, 20 times 33% typical resistance to solvent mil-std-202,method 215 no change vibration mil-std-202,method 201 no change ambient operating conditions : - 40 c to 85 c maximum surface temperature of the device in the tripped state is 125 c test average time current curves 0.001 0.01 0.1 1 10 100 0.1 1 10 100 current in amperes time in second 050 100 150 200 derating curves for smd2018 0 20 40 60 80 100 120 140 160 -40 -20 0 20 40 60 80 temperature (c) percentage of derated current
surface mount resettable ptcs revision october 18, 2015 3 / 3 @ un semiconductor co., ltd. 2015 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. a b c device nominal nominal nominal 2018serie s 3.4 1.5 4.6 the dimensio n in the table belo w p rovide the recommended pad layout for each smd1812 device a b c d part number min. max. min. max. min. max. min. max. SMD2018-030 4.72 5.44 4.22 4.93 0.60 1.10 0.30 0.95 smd2018-050 4.37 4.73 3.07 3.41 0.50 1.00 0.30 0.95 smd2018-100 4. 37 4.73 3 . 07 3. 41 0. 50 1. 00 0. 30 0.95 smd2018-150 4.37 4.73 3.07 3.41 0.50 1.00 0.30 0.95 smd2018-200 4. 37 4.73 3 . 07 3. 41 0. 40 0. 90 0. 30 0.95 dimensions uni t: mm pad layouts unit: mm warning use pptc beyond the maximum ratings or improper use may result in device damage and possible electrical arcing and flame. pptc are intended for protection against occasional over current or over temperature fault conditions and should not be used when repeated fault conditions or prolonged trip events are anticipated. device performance can be impacted negatively if devices are handled in a manner inconsistent with recommended electronic, thermal, and mechanical procedures for electronic components. use pptc with a large inductance in circuit will generate a circuit voltage (l di/dt) above the rated voltage of the pptc. avoid impact pptc device its thermal expansion like placed under pressure or installed in limited space. contamination of the pptc material with certain silicon based oils or some aggressive solvents can adversely impact the performance of the devices. pptc smd can be cleaned by standard methods. requests that customers comply with our recommended solder pad layouts and recommended reflow profile. improper board layouts or reflow profile could negatively impact solderability performance of our devices.
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